The invention relates to a method for forming a pattern of a semiconductor device, and more specifically, to a method for forming a pattern of a semiconductor device that has a profile with reduced distortion in a process for manufacturing a high density flash memory device (e.g., NAND) using a spacer patterning technology.
Recently, a semiconductor technology has been rapidly developed in order to store the ever increasing amount of information, promptly process or transmit information, and construct a simpler information communication network in line with the 21th century information communication society. Particularly, due to rapid popularization of information media such as computers, ongoing research has focused on development of process equipment or process techniques for manufacturing a semiconductor device that has a large capacity with a low manufacturing cost without degrading electric characteristics while components are fabricated to be smaller has been made.
Particularly, the demand of nonvolatile flash memory devices that can program and erase programs electrically and do not require a refresh function for re-writing data with a given cycle has increased.
Information stored in the cells of the flash memory device is not lost even when power is shut off. Therefore, the flash memory device has been applied to the memory card. Common types of flash memory device includes a NAND flash memory device and a NOR flash memory device.
The NAND flash memory has a cell region and a peripheral circuit region. More specifically, the NAND flash memory device comprises a memory cell array that includes a plurality of bit lines, a plurality of word lines intersected orthogonally with the bit lines, and a plurality of strings. Each string includes a plurality of memory cells, a source select transistor (SST) and a drain select transistor (DST). The SST and DST are connected serially to the memory cells and are used for selecting each string. The drain select transistor is selected by a drain select line (DSL), and the source select transistor is selected by a source select line (SSL). A source of the source select transistor included in each string is grounded by a common source line (CSL). The peripheral circuit region includes a PMOS transistor and a NMOS transistor.
The NOR flash memory device comprises of a plurality of memory cells and a cell region that includes bit lines and common source lines. One memory cell is interposed between the bit line and the common source line. As a result, the NAND flash memory device shows higher integration than the NOR flash memory device, but requires a higher cell current.
As semiconductor devices becomes smaller, it becomes important to control a critical dimension of a pattern. However, it is difficult to form a line/space (L/S) pattern having a critical dimension of less than 40 nm by a single exposing process due to a resolution limit of an ArF exposer used in a current process for forming a pattern of a semiconductor device. Particularly, it is difficult to form a L/S pattern of less than 30 nm with a high index fluid material and an exposure having a high numeral aperture. In order to improve the formation of the L/S pattern, an exposure light source with short wavelength like Extreme Ultra Violet (EUV) (13.4 nm), and an exposer and resist suitable for the light source are being developed. However, they are still insufficient for the manufacturing of semiconductor devices.
As a result, a K1 factor of the conventional exposer is lowered to improve a resolution of a photolithography technology and enlarge a process margin. A double patterning technology is developed with an improved resolution. The double patterning technology includes a double exposing and etching technology and a spacer patterning technology.
The spacer patterning technology is a self-alignment technology that includes a mask process performed once to form a pattern, thereby preventing mis-alignment. The spacer patterning technology includes a positive method and a negative method.
The positive spacer patterning method comprises: forming a mask pattern for a word line over an underlying layer of a cell region; etching the underlying layer with the mask pattern as an etching mask to form a partition; forming a spacer pattern at sidewalls of the partition; performing a cutting mask process for removing the partition and separating the line end portion of the spacer pattern; and forming a pad pattern in core and peripheral regions. As a result, the process steps of the positive spacer patterning method are complicated. Moreover, since the spacer pattern having an asymmetrical structure is used as an etching mask, it is difficult to adjust a critical dimension of a lower underlying layer by a difference of an etching process condition.
In order to reduce the process steps and improve the above shortcoming, a simplified spacer patterning method is developed. Hereinafter, FIGS. 1a to 1f show the simplified spacer patterning method in detail.
An underlying layer 11 that includes a dielectric film (not shown) consisting of an oxide film-nitride film-oxide film (ONO), a gate polysilicon layer (not shown), a tungsten conductive layer (not shown), a capping oxide film (not shown) and a gate mask film (not shown) is formed over a substrate that includes a device isolation film (ISO).
A first mask film 13, a second mask film 15, a third mask film 17 and an antireflection film 19 are sequentially deposited over the underlying layer. The first mask film is selected from the group including an oxide film, and the second mask film includes an amorphous carbon layer.
Referring to FIG. 1a, a photoresist film (not shown) is coated over the antireflection film 19. A photolithography process is performed on the photoresist film using a cell exposure mask. The cell exposure mask includes a light transmitting region having a pitch twice larger than a device pitch, thereby obtaining a first photoresist pattern 21 for a word line. The first photoresist pattern 21 is formed to have n protrusions when the number of final word lines is 2n. 
Referring to FIG. 1b, the antireflection film 19 is etched with the first photoresist pattern 21 as an etching mask to form a stack pattern consisting of an antireflection pattern 19-1 and a first photoresist pattern 21.
Referring to FIG. 1c, a spacer forming material (not shown) is deposited over substrate comprising the stack pattern. An etch-back process is performed to form a spacer 23 at sidewalls of the stack pattern.
Referring to FIG. 1d, an O2 plasma ashing process is performed on the resulting structure to remove the stack pattern, thereby obtaining 2n spacer patterns 23-1.
A second photoresist pattern (not shown) that exposes the end portion of the spacer pattern 23-1 is formed. An etching process (not shown) for separating the end portions of the spacer patterns 23-1 is performed with the second photoresist pattern as an etching mask.
Referring to FIG. 1e, a third photoresist film (not shown) is formed over a substrate comprising the separated spacer patterns 23-1. A lithography process is performed on the third photoresist film (not shown) to form a pad mask pattern 25 for SSL or DSL in the peripheral circuit region.
Referring to FIG. 1f, the first, second and third mask films 13, 15, 17 are etched with the spacer pattern 23-1 and the pad mask pattern 25 as etching masks until the underlying layer 11 is exposed, thereby obtaining a stack pattern including a first mask pattern 13-1 and a second mask pattern 15-1. The third mask film is removed by the etching process.
The lower underlying layer 11 is etched with the stack pattern as an etching mask to obtain a control word line pattern (not shown) of the NAND flash memory.
It is difficult to control a critical dimension of a gate string pattern in a conventional method for fabricating a flash device. Specifically, in the conventional method, when a photoresist pattern for a word line is formed over a cell region, it is difficult to form a photoresist pattern having a uniform critical dimension due to a difference of a peripheral pattern density between photoresist patterns of the center region and photoresist patterns of the edge region in the cell region. That is, the photoresist pattern of the edge region is affected by a surface tension effect of a capillary force of a developing solution during a developing process for forming a photoresist pattern. As a result, the photoresist pattern is bent toward the center direction or collapsed as shown in FIG. 2. For example, the critical dimension of the edge string pattern (Nos. 13 and 17) has a difference of about 7 nm from the critical dimension (0 nm) of the center pattern (see FIG. 3). The edge pattern is weaker from defocus than the center pattern, so that a margin of the depth of focus (hereinafter, referred to as “DOF”) is reduced to a range of 0±06 μm (see FIG. 4). As a result, a profile of the string pattern and the critical dimension uniformity are degraded during a subsequent etching process using the photoresist pattern as an etching mask.
Meanwhile, the height of the spacer pattern used as an etching mask when lower films are etched is determined by the height of the photoresist pattern. In order to perform the simplified spacer patterning method smoothly, the height of the photoresist pattern is required to be higher. However, the edge photoresist pattern is bent, so that the critical dimension difference is increased and DOF of the string is reduced.